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ch7308b 201 - 0000 - 0 6 4 rev. 3. 0 , 0 5 / 1 1 /20 11 1 ch7308 b sdvo 1 lvds transmitter features general description ? single/dual lvds transmitter up to 165mpixels/s ? support resolution s up to 1600x1200 (1920x1200 with reduced blanking) ? lvds low jitter pll accepts spread spectrum input ? lvds 18 - bit and 24 - bit o utputs ? 2d dither engine ? panel protection and power sequencing ? high - speed sdvo 1 serial (1g~2gbps) ac - coupled differential rgb inputs ? low voltage interface support to graphics device ? programmable power management ? fully programmable through serial port ? config uration through opcodes 1 ? complete windows driver support ? boundary scan support ? offered in a 64 - pin lqfp package the ch 7308b is a display controller device, which accepts digital graphics input signals, upscales, encodes, and transmits data through an lvds transmitter to a lcd panel. this device accepts one channel of rgb data over three pairs of serial data ports. the lvds transmitter includes a low jitter pll to generate a high frequency serialized clock and all circuitry required to upscale, encode, se rialize and transmit data. t he ch7308b supports a maximum pixel rate of 165mp/s. the lvds transmitter includes a panel fitting up - scaler and a programmable dither function to support 18 - bit lcd panels. data is encoded into commonly used formats, includi ng those specified in the openldi and spwg specifications. serialized data is outputted on three to eight differential channels. 1 intel proprietary figure 1 : functional block diagram chrontel data latch, serial to parallel clock driver serial port/ power control sdvo character decoder up-scaler dither lvds encoder fifo lvds serializer lvds driver lvds pll ldc[3:0],ldc*[3:0] ll1c,ll1c* ldc[7:4],ldc*[7:4] ll2c,ll2c* sdvo_r(+/-) sdvo_g(+/-) sdvo_b(+/-) sdvo_clk(+/-) reset* as spc spd sc_prom sd_prom sc_ddc sd_ddc vswing stall(+/-) generator/ power sequencing xtal xi/fin, xo sdvo_stall(+/-) enavdd enabkl
chrontel ch7 3 0 8b 2 201 - 00 00 - 0 6 4 rev. 3. 0 , 0 5 / 1 1 /20 11 table of contents 1.0 pin assignment ................................ ................................ ................................ ............................. 3 1.1 package diagram ................................ ................................ ................................ ................................ ....... 3 1.2 pin description ................................ ................................ ................................ ................................ .......... 4 2.0 functional description ................................ ................................ ................................ ................. 6 2.1 input interface ................................ ................................ ................................ ................................ ............ 6 2.2 automatic panel - f itting ................................ ................................ ................................ ............................. 8 2.3 emission reduction clock ................................ ................................ ................................ ......................... 9 2.4 dithering ................................ ................................ ................................ ................................ .................... 9 2.5 power sequ encing ................................ ................................ ................................ ................................ ..... 9 2.6 panel protection ................................ ................................ ................................ ................................ ....... 10 2.7 command interface ................................ ................................ ................................ ................................ . 10 3.0 register control ................................ ................................ ................................ .......................... 13 4.0 electrical specifications ................................ ................................ ................................ ............. 13 4.1 absolute maximum ratings ................................ ................................ ................................ .................... 13 4.2 recommended operating conditions ................................ ................................ ................................ ...... 13 4.3 electrical characteristics ................................ ................................ ................................ ......................... 14 4.4 dc specifications ................................ ................................ ................................ ................................ .... 14 4.5 ac specifications ................................ ................................ ................................ ................................ .... 16 4.6 lvds output specifications ................................ ................................ ................................ ................... 17 4.7 lvds output timing ................................ ................................ ................................ .............................. 19 5.0 package dimensions ................................ ................................ ................................ ................... 20 6.0 revision history ................................ ................................ ................................ .......................... 21
chrontel ch7 3 0 8b 201 - 0000 - 0 6 4 rev. 3. 0 , 0 5 / 1 1 /20 11 3 1.0 pin assignment 1.1 package diagram figure 2 : 64 pin lqfp pin out (top view) b 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 2 6 2 7 2 8 2 1 2 2 2 3 2 4 2 5 2 9 3 0 3 1 3 2 chrontel l d c 7 * l g n d l d c 5 * l d c 6 * l v d d l d c 5 l d c 6 d g n d l g n d l d c 4 l d c 4 * l l 2 c * l d c 7 l v d d agnd _ pll sd _ prom sc _ ddc sd _ ddc xo xi sc _ prom dgnd spd enavdd reset * spc as l l 2 c a g n d s d v o _ b - s d v o _ r - a g n d s d v o _ g + s d v o _ g - a v d d s d v o _ b + s d v o _ c l k + s d v o _ c l k - dvdd s d v o _ r + avdd _ pll sdvo _ stall - b s c a n r e s e r v e d a v d d 64 63 62 61 60 59 58 57 1 7 1 8 1 9 2 0 t e s t d v d d sdvo _ stall + ldc 0 * ldc 0 lvdd ldc 1 * ldc 1 lgnd ldc 2 * ldc 2 lvdd ll 1 c * ll 1 c lgnd ldc 3 * 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 ldc 3 v s w i n g enavbkl ch7308
chrontel ch7 3 0 8b 4 201 - 00 00 - 0 6 4 rev. 3. 0 , 0 5 / 1 1 /20 11 1.2 pin description table 1 : pin description pin # type symbol description 4 in reset* reset* input (internal pull - up) when this pin is low, the device is held in the power - on reset condi tion. when this pin is high, reset is controlled through the serial port interface. 5 in as address select (internal pull - up) this pin determines the serial port address of the device (0,1,1,1,0,0,as*,0). 6 in/out spc serial port clock input this pin functions as the clock input of the serial port interface and operates with from 0 to 2.5v. this pin requires an external 4k ? - 9k ? pull up resistor to 2.5v 7 in/out spd serial port data input/output this pin functions as the bi - directional data pin of the serial port interface and operates with inputs from 0 to 2.5v. outputs are driven from 0 to 2.5v. this pin requires an external 4k ? - 9k ? pull up resistor to 2.5v. 9 in/out sd_prom routed data output to prom this pin functions as the bi - directional data pin of the serial port interface for the external 5v serial eeprom used for add2 card designs. this pin requires an external 5.6k pull - up resistor to the desired high state voltage. leave open if unused. 10 in/out sc_prom routed clock output to pr om this pin functions as the clock bus of the serial port interface for the external 5v serial eeprom used for add2 card designs. this pin requires an external 5.6k pull - up resistor to the desired high state voltage. leave open if unused. 11 in/out sd_ddc routed serial port data output to ddc this pin functions as the bi - directional data pin of the serial port to the ddc of the receiver. this pin requires an external 4 C 9k ? pull - up resistor to the desired high state voltage. leave open if unused. 12 in/o ut sc_ddc routed serial port clock output to ddc this pin functions as the clock bus of the serial port to the ddc of the receiver. this pin requires an external 4 C 9k ? pull - up resistor to the desired high state voltage. leave open if unused. 2 out enav dd panel power enable enable lcd panel vdd (2.5v). 1 out enabkl backlight enable enable backlight of lcd panel (2.5v). 63 in bscan bscan (internal pull low ) this pin should be left open or be pulled low with 10 k ? resistor . 50 out test test internal te st pin to monitor the state of the enexbuf (external buffer enable) signal. see tb49 for details. if the enexbuf signal does not need to be monitored, this pin may be left open. 64 in reserved reserved this pin should be left open
chrontel ch7 3 0 8b 201 - 0000 - 0 6 4 rev. 3. 0 , 0 5 / 1 1 /20 11 5 pin# type symbol de scription 51, 52, 54, 55, 57, 58 in sdvo_r+/ - sdvo_g+/ - sdvo_b+/ - sdvo data channel inputs these pins accept 3 ac - coupled differential pair of inputs from the digital video port of a graphics controller. these 3 pairs of inputs can be r, g, b. the differ ential p - p input voltage has a maximum value of 1.2v, with a minimum value of 175mv. 60, 61 in sdvo_clk+/ - differential clock input associated with sdvo data channel (sdvo_r+/ - , sdvo_g+/ - , sdvo_b+/ - ) the range of this clock pair is 100~200mhz. for specif ic pixel rates in specific modes, this clock pair will run at an integer multiple of the pixel rate. refer to section 2.1.2 for details. 47, 48 out sdvo_stall+/ - stall signal pair associated with sdvo data channel (sdvo_r +/ - , sdvo_g+/ - , sdvo_b+/ - ) this differential pair is used as a stall indication for a vga controller, which is capable of driving out sdvo_r+/ - , sdvo_g+/ - , sdvo_b+/ - data. when toggling between 100mhz and 200mhz, the stall indication state is asserted (?1? value); when not toggling at all the state is de - asserted (?0? value). the differential p - p output voltage has a maximum value of 1.2v, with a minimum value of 175mv. 36, 37 out ll1c, ll1c* lvds differential clock channel 1 17, 18 out ll2c, ll2c* lvds differential clock channel 2 33, 39, 42, 45, 34, 40, 43, 46 out ldc[3:0], ldc*[3:0] lvds differential data[3:0] 20, 23, 26, 29, 21, 24, 27, 30 out ldc[7:4], ldc*[7:4] lvds differential data [7:4] 32 in vswing lvds swing control this pin sets the swing level of the lvds outputs. a 2.4kohm resistor should be connected between this pin and lgnd using short and wide traces. 14 in xi/fin crystal input/external reference input a parallel resonant 14.31818 mhz crystal (+/ - 1000 ppm) should be attached between this pin and xo. alternatively, an external cmos compatible clock may be used to drive the xi/fin input. 15 out xo crystal output a parallel resonant 14.31818 mhz crystal (+/ - 1000 ppm ) should be attached between this pin and xi/fin. however, if an exte rnal cmos clock is attached to xi/fin, xo should be left open. 16, 49 power dvdd digital supply voltage (2.5v) 13, 31 power dgnd digital ground 19, 25, 38, 44 power lvdd lvds supply voltage (3.3v) 22, 28, 35, 41 power lgnd lvds ground 56, 62 power avd d analog supply voltage (2.5v) 53, 59 power agnd analog ground 3 power avdd_pll lvds pll supply voltage (3.3v) 8 power agnd_pll lvds pll ground
chrontel ch7 3 0 8b 6 201 - 00 00 - 0 6 4 rev. 3. 0 , 0 5 / 1 1 /20 11 2.0 functional description 2.1 input interface one pair of differential clock signals and three differen tial pairs of signals (r/g/b) form one channel data. the input data is 10 - bit serialized data. input data operates from 1ghz~2ghz and is a 10x multiple of the clock rate (sdvo_clk+/ - ). the ch 7308b first de - serializes the input into 10 - bit parallel data wit h synchronization and alignment then the 10 - bit characters are mapped into 8 - bit color data or control data (hsync, vsync, de). 2.1.1 interface voltage levels all differential sdvo pairs are ac coupled differential signals. therefore, there is not a specifie d dc signal level for the signals to operate at. the minimum differential p - p input voltage is 175mvand the maximum differential p - p input voltage is 1.2v. the minimum differential p - p output voltage is 0.247v and the maximum differential p - p output voltag e is 0.453v. 2.1.2 input clock and data timing a data character is transmitted least significant bit first. the beginning of a character is noted by the falling edge of the sdvo_clk+ edge. the skew among input lanes is required to be no larger than 2ns. the clock rate must be between 100mhz~200mhz. the pixel rate can be 25mp/s~165mp/s. the pixel rate and the clock rate do not have to be equal. the clock rate is a multiple of the pixel rate (1x, 2x or 4x depending on the pixel rate) such that the clock rate re mains within the 100mhz~200mhz range. in the condition that the clock rate is running at a multiple of the pixel rate, there isn?t enough pixel data to fill the data channels. dummy fill characters (?0001111010?) are used to stuff the data stream. the ch 73 08b supports the following clock rate multipliers and fill patterns shown in table 2 . table 2 : ch 7308b supported pixel rates, clock rates, data transfer rates and fill patterns pixel rate clo ck rate C 25~50 mp/s 100~200 mhz C 4xpixel rate data, fill, fill, fill 1.00~2.00 ghz C 10xclock rate 50~100 mp/s 100~200 mhz C 2xpixel rate data, fill 1.00~2.00 ghz C 10xclock rate 1 00~165 mp/s 100~200 mhz C 1xpixel rate data 1.00~2.00 ghz C 10xclock rate 2.1.3 synchronization synchronization and channel - to - channel deskewing is facilitated by the transmission of special characters during the blank period. the ch 7308b synchronizes during the initialization period and subsequently uses the blank periods to re - synch to the data stream. 2.1.4 lvds - output table 3 : signal mapping for single lvds channel 18 - bit spwg / 18 - bit openldi 24 - bit spwg / 24 - bit openldi ldc[0](1) r0 / r0 r0 / r2 ldc[0](2) r1 / r1 r1 / r3 ldc[0](3) r2 / r2 r2 / r4 ldc[0](4) r3 / r3 r3 / r5 ldc[0](5) r4 / r4 r4 / r6 ldc[0](6) r5 / r5 r5 / r7 ldc[0](7) g0 / g0 g0 / g2 ldc[1](1) g1 / g1 g1 / g3 ldc[1](2) g2 / g2 g2 / g4 ldc[1](3) g3 / g3 g3 / g 5 ldc[1](4) g4 / g4 g4 / g6
chrontel ch7 3 0 8b 201 - 0000 - 0 6 4 rev. 3. 0 , 0 5 / 1 1 /20 11 7 ldc[1](5) g5 / g5 g5 / g7 ldc[1](6) b0 / b0 b0 / b2 ldc[1](7) b1 / b1 b1 / b3 ldc[2](1) b2 / b2 b2 / b4 ldc[2](2) b3 / b3 b3 / b5 ldc[2](3) b4 / b4 b4 / b6 ldc[2](4) b5 / b5 b5 / b7 ldc[2](5) hsync / hsync hsync / hsync ldc[2](6) vsync / vsync vsync / vsync ldc[2](7) de / de de / de ldc[3](1) r6 / r0 ldc[3](2) r7 / r1 ldc[3](3) g6 / g0 ldc[3](4) g7 / g1 ldc[3](5) b6 / b0 ldc[3](6) b7 / b1 ldc[3](7) res / res table 4 : signal mappin g for dual lvds channel 18 - bit spwg / 18 - bit openldi 24 - bit spwg / 24 - bit openldi ldc[0](1) ro0 / ro0 ro0 / ro2 ldc[0](2) ro1 / ro1 ro1 / ro3 ldc[0](3) ro2 / ro2 ro2 / ro4 ldc[0](4) ro3 / ro3 ro3 / ro5 ldc[0](5) ro4 / ro4 ro4 / ro6 ldc[0](6) ro5 / ro5 ro5 / ro7 ldc[0](7) go0 / go0 go0 / ro2 ldc[1](1) go1 / go1 go1 / ro3 ldc[1](2) go2 / go2 go2 / go4 ldc[1](3) go3 / go3 go3 / go5 ldc[1](4) go4 / go4 go4 / go6 ldc[1](5) go5 / go5 go5 / go7 ldc[1](6) bo0 / bo0 bo0 / bo2 ldc[1](7) bo1 / bo1 bo1 / bo3 ldc[2](1) bo2 / bo2 bo2 / bo4 ldc[2](2) bo3 / bo3 bo3 / bo5 ldc[2](3) bo4 / bo4 bo4 / bo6 ldc[2](4) bo5 / bo5 bo5 / bo7 ldc[2](5) hsync / hsync hsync / hsync ldc[2](6) vsync / vsync vsync / vsync ldc[2](7) de / de de / de ldc[3](1) ro6 / ro0 ldc[3](2) ro7 / ro1 ldc[3](3) go6 / ro0 ldc[3](4) go7 / go1 ldc[3](5) bo6 / bo0 ldc[3](6) bo7 / bo1 ldc[3](7) res / res ldc[4](1) re0 / re0 re0 / re2 ldc[4](2) re1 / re1 re1 / re3 ldc[4](3) re2 / re2 re2 / re4 ldc[4](4) re3 / re3 re3 / re5 ldc[4](5) re4 / re4 re4 / re6 ldc[4](6) re5 / re5 re5 / re7 ldc[4](7) ge0 / ge0 ge0 / ge2
chrontel ch7 3 0 8b 8 201 - 00 00 - 0 6 4 rev. 3. 0 , 0 5 / 1 1 /20 11 ldc[5](1) ge1 / ge1 ge1 / ge3 ldc[5](2) ge2 / ge2 ge2 / ge4 ldc[5](3) ge3 / ge3 ge3 / ge5 ldc[5](4) ge4 / ge4 ge4 / ge6 ldc[5](5) ge5 / ge5 ge5 / ge7 ldc[5] (6) be0 / be0 be0 / be2 ldc[5](7) be1 / be1 be1 / be3 ldc[6](1) be2 / be2 be2 / be4 ldc[6](2) be3 / be3 be3 / be5 ldc[6](3) be4 / be4 be4 / be6 ldc[6](4) be5 / be5 be5 / be7 ldc[6](5) hsync / lctle hsync / lctle ldc[6](6) vsync / lctlf vsync / lct lf ldc[6](7) de / la6rl de / la6rl ldc[7](1) re6 / re0 ldc[7](2) re7 / re1 ldc[7](3) ge6 / re0 ldc[7](4) ge7 / re1 ldc[7](5) be6 / be0 ldc[7](6) be7 / be1 ldc[7](7) res 2.2 automatic panel - fitting serialized input data, sync and cloc k signals are input to the ch 7308b from the graphics controller?s serial digital video output port. input is through three differential data pairs and one differential clock pair . the data rate is in the range of 1.0~2.0ghz. the clock rate, independent fro m the pixel rate, is 1/10 of the data rate, resulting in the range of 100m~200mhz. horizontal sync and vertical sync information are embedded in the data stream. given the panel information (output timing information), the ch 7308b can automatically fit t he output timing to the panel. the up - scaler in the ch 7308b supports but is not limited to the following lvds panel sizes: table 5 : popular panel sizes wuxga 1920x1200 ( reduce d blanking) uxga 1600x1200 w ide sxga+ 1680x1050 sxga+ 1400x1050 1360x1024 wsxga 1440x900 sxga 1280x1024 1280x960 wxga 1366x768 xga 1024x768 1024x600 svga 800x600 the ch 7308b is capable of up - scaling images containing 1400 active horizontal pixels or less to the nati ve resolution of the supported lvds panel. for resolutions containing more than 1400 horizontal pixels, no up - scaling will be done. the up - scaler periodically sends a pair of sdvo_stall(+/ - ) signals to the graphics controller to halt the transmission of on e line of active video data. when the sdvo_stall(+/ - ) signals t oggle between 100mhz and 200mhz, this is interpreted as asking for next line of video data to be stalled; not toggling at all is considered as asking for the next line of video data to be sen t. the up - scaler performs 2d interpolation of the graphics input data and does not change the pixel rate between the input and the output. the 2d interpolation consists of programmable non - linear functions. the maximum pixel rate s upported by the up - scaler is 200 mp/s.
chrontel ch7 3 0 8b 201 - 0000 - 0 6 4 rev. 3. 0 , 0 5 / 1 1 /20 11 9 2.3 emission reduction clock lvds output can support a ? 2.5% spreading in the output clock to reduce emi emissions. the frequency and the amplitude of the spreading triangle waveform can be programmed via opcode commands. 2.4 dithering the dithe r engine in the ch 7308b converts 24 - bit per pixel rgb data to 18 - bit per pixel rgb data before sending the data to the lvds encoder. the maximum pixel rate supported is 165mp/s. this feature supports 18 - bit lvds panels only. 2.5 power sequencing the ch 7308b conforms to the spwg requirements on power sequencing. the timing specification shown in figure 4 is a superset of the requirements dictated by the spwg specification. the timing parameters can be programmed to different values via opcode commands to s uit the timing requirements defined by the particular panel specifications to be used. figure 3 : power sequencing table 6 : power sequencing range increment t1 1 - 1023 ms 1 ms t2 1 - 1023 ms 1ms t3 1 - 102 3 ms 1ms t4 1 - 1023 ms 1 ms t5 1 - 1023 ms 1ms the power - on sequence begins when the lvds software registers are set properly via opcode commands and the internal pll lock detection circuit, the internal sync detection circuit, and the xclk detection circ uit (see section 2.6) indicate that hsync, vsync and xclk are stable. the power - off sequence begins when any of the detection circuits indicates instability in the timing signals (see section 2.6), or through opcode programming. once the power - off sequenc e starts, the internal state machine will complete the power - off sequence and power - on sequence is allowed only after t5 is passed. to verify the t1 C t5 lvds panel power sequencing, please see tb49 for more details. lvds clocks enavdd enabkl lvds data t 1 t 3 t 2 t 4 t 5 enexbuf valid data valid clock tristate or gnd tristate or gnd
chrontel ch7 3 0 8b 10 201 - 00 00 - 0 6 4 rev. 3. 0 , 0 5 / 1 1 /20 11 2.6 panel protection damage to the lcd panel may occur if either hsync or vsync signals are absent from the lvds link. this situation can happen when there is a catastrophic failure in the pc or the graphics system. the ch 7308b is designed to prevent damage to the panel under such a failure. i f the system fails, the ch 7308b does not expect any software instruction from the graphics controller to power down the panel. detection circuits are used to monitor the three timing signals C hsync, vsync and xclk. if any one, combination of, or all of th ese signals becomes unstable or missing, the ch 7308b will commence power down sequencing. the power up sequence can occur only if there are no missing hsync and vsync, the input clock is available, the pll clock is stable and the setactiveoutput opcode is called. the power down sequence is initiated if one of those conditions fails. the panel protection circuitry is comprised of the pll lock detection block, which detects an unstable clock from the lvds pll, the sync detection block, which detects missin g inputs hsync and vsync, and the clock detection block, which detects missing input clock. the sync detection block consists of counters to count hsync and vsync pulses. one counter is used to count the number of hsync pulses per frame over 3 frames. the end counts for all 3 frames must be equal to enable the power up sequence. in addition, the sync detection block checks for the presence of vsync and hsync. if vsync is missing for 2 frames or if hsync is missing for 32us, the power up sequence is disable d. conversely, if the panel has been enabled and the number of hsync pulses per frame is different over 3 frames, vsync is missing for 2 frames, or hsync is missing for 32us, the ch 7308b will go into a power down sequence. the pll lock detection, sync det ection and clock detection blocks can be defeated independently. opcode commands are supported for these features. the power up sequence can also occur if the panel protection circuitry is defeated. 2.7 command interface communication is through a two - wire path, control clock (spc) and data (spd). the ch 7308b accepts incoming control clock and data from a graphics controller, and is capable of redirecting that data stream to the add2 card prom, ddc, or ch 7308b internal registers. the control bus is able to r un up to 1mhz. figure 4 : control bus switch upon reset, the default state of the control bus direction switch is to redirect the control bus interface to the add2 prom. at this stage, the ch 7308b observes the control bus traffic. if the observing logic sees a control bus transaction destined for the internal registers (device address 70h or 72h), it disables the prom output pairs, and switches to internal registers. in the condition that traffic is to the internal registers, an opcode command is used to set the redirection circuitry to the appropriate destination (add2 prom or ddc). redirecting the traffic to internal registers while at the stage of traffic to ddc occurs on observing a stop after a start on the control bus. internal device registers ddc prom control bus from vga observer control the switch on/off default position
chrontel ch7 3 0 8b 201 - 0000 - 0 6 4 rev. 3. 0 , 0 5 / 1 1 /20 11 11 2.7.1 nand tree test ch 7308b provides nand tree testing to verify io cell functions at the pc board level. this test will check the interconnect between the chip?s i/o and the printed circuit board for faults (soldering, bent leads , open printed circuit board traces, etc.). the nand tree test is a simple serial logic which turns all io cell signals to input mode, connects all inputs with nand gates as shown in figure 6 and switches each signal to high or low according to the sequenc e in table 7 . the test results are then passed out of pin 48 (sdvo_stall - ). this test is enabled when the bscan pin (pin 63) is set to 1. figure 5 : nand tree connection testing sequence set bscan = 1; (internal weak pull low) set all signals listed in table 7 to 1. set all signals listed in table 7 to 0, toggle one by one with a suggested time period of 200 ns. pin 48 will change its value each time an input value changed.
chrontel ch7 3 0 8b 12 201 - 00 00 - 0 6 4 rev. 3. 0 , 0 5 / 1 1 /20 11 table 7 : signal order in the nand tree testing order pin name lqfp pin 1 enabkl 1 2 enavdd 2 3 reset* 4 4 as 5 5 spc 6 6 spd 7 7 sd_prom 9 8 sc_prom 10 9 sd_dd c 11 10 sc_ddc 12 11 xi 14 12 xo 15 13 ll2c 17 14 ll2c* 18 15 ldc7 20 16 ldc7* 21 17 ldc6 23 18 ldc6* 24 19 ldc5 26 20 ldc5* 27 21 ldc4 29 22 ldc4* 30 23 ldc3 33 24 ldc3* 34 25 ll1c 36 26 ll1c* 37 27 ldc2 39 28 ldc2* 40 29 ldc1 42 30 l dc1* 43 31 ldc0 45 32 ldc0* 46 33 sdvob_stall+ 47 34 sdvob_stall - 48
chrontel ch7 3 0 8b 201 - 0000 - 0 6 4 rev. 3. 0 , 0 5 / 1 1 /20 11 13 3.0 register control the ch 7308b is controlled by using intel opcodes through the serial port. the serial bus uses only the spc clock to latch data into registers, a nd does not use any internally generated clocks so that the device can be written to in all power down modes. the device will retain all register values during power down modes. for details regarding intel ? sdvo opcodes, please contact intel ? . 4.0 electri cal specifications 4.1 absolute maximum ratings symbol description min typ max units all 2.5v power supplies relative to gnd all 3.3v power supplies relative to gnd - 0.5 - 0.5 3.0 5.0 v t sc analog output short circuit duration indefinite sec t amb ambi ent operating temperature - 4 0 85 ? c t stor storage temperature - 65 150 ? c t j junction temperature 150 ? c t vps1 vapor phase soldering (5 seconds) 260 ? c t vps2 vapor phase soldering (11 seconds) 245 ? c t vps3 vapor phase soldering (60 seconds) 225 ? c note: 1) stresses greater than those listed under absolute maximum ratings may cause permanent damage to the device. these are stress ratings only. functional operation of the device at these or any other conditions above those indicated under the normal operating condition of this specification is not recommended. exposure to absolute maximum rating conditions for extended periods may affect reliability. the temperature requirements of vapor phase soldering apply to all standard and lead free part s. 2) the device is fabricated using high - performance cmos technology. it should be handled as an esd sensitive device. voltage on any signal pin that exceeds the power supply voltages by more than 0.5v can induce a destructive latchup. 4.2 recommended operat ing conditions symbol description min typ max units avdd analog power supply voltage 2.375 2.5 2.625 v avdd_pll analog pll power supply voltage 3.100 3.3 3.500 v dvdd digital power supply voltage 2.375 2.5 2.625 v lvdd lvds power supply 3.100 3.3 3.5 00 v vdd33 generic for all 3.3v supplies 3.100 3.3 3.500 v vdd25 generic for all 2.5v supplies 2.375 2.5 2.625 v ambient operating temperature - 4 0 85 ? c
chrontel ch7 3 0 8b 14 201 - 00 00 - 0 6 4 rev. 3. 0 , 0 5 / 1 1 /20 11 4.3 electrical characteristics (operating conditions: t a = - 4 0 ? c C + 85 ? c, vdd25 =2.5v ? 5%, vdd33= 3.3v ? 5%) symbol description min typ max units i vdd25 total vdd25 supply current (2.5v supplies) (no upscaler) 170 200 ma i vdd33 total vdd33 supply current (3.3v supply) (no upscaler) 70 85 ma i vdd25up total vdd25 supply current (2.5v supplies) (with upscaler enabled) 270 340 ma i vdd33up total vdd33 supply current (3.3v supply) (with upscaler enabled) 70 85 ma i pd total power down current (all supplies) 30 ua 4.4 dc specifications symbol description test condition min typ max unit v rx - diffp - p s dvo receiver differential input peak to peak voltage v rx - diffp - p = 2 * ? v rx - d+ - v rx - d - ? 0.175 1.200 v z rx - diff - dc sdvo receiver dc differential input impedance 80 100 120 ? z rx - com - dc sdvo receiver dc common mode input impedance 40 50 60 ? z rx - com - i nitial - dc sdvo receiver initial dc common mode input impedance impedance allowed when receiver terminations are first turned on 5 50 60 ? v stall - diffp - p sdvo stall differential output peak to peak voltage v stall - diffp - p = 2 * ? v stall - d+ - v stall - d - ? 0.8 1.200 v v sdol 1 spd (serial port data) output low voltage i ol = 2.0 ma 0.4 v v spih 2 serial port (spc, spd) input high voltage 2.0 vdd25+ 0.5 v v spil 2 serial port (spc, spd) input low voltage gnd - 0.5 0.4 v v hys hysteresis of serial port inputs 0.25 v v ddcih ddc serial port input high voltage 4.0 vdd5 + 0.5 v v ddcil ddc serial port input low voltage gnd - 0.5 0.4 v v promih prom serial port input high voltage 4.0 vdd5 + 0.5 v v promil prom serial port input low voltage gnd - 0 .5 0.4 v v sd _ ddcol 3 spd (serial port data) output low voltage from sd_ddc (or sd_eprom) input is v inl at sd_ddc or sd_eprom. 4.0k ? pullup to 2.5v. 0.9*v inl + 0.25 v
chrontel ch7 3 0 8b 201 - 0000 - 0 6 4 rev. 3. 0 , 0 5 / 1 1 /20 11 15 symbol description test condition min typ max unit v ddcol 4 sc_ddc and sd_ddc output low voltage input is v inl at spc and spd. 5.6k ? pullup to 5.0v. 0.933*v inl + 0.35 v v epromol 5 sc_eprom and sd_eprom output low voltage input is v inl at spc and spd. 5.6k ? pullup to 5.0v. 0.933*v inl + 0.35 v v asih as input high voltage 2.0 vdd25 + 0.5 v v asil as input low voltage gnd - 0.5 0 .5 v i aspu as pull up current v in = 0v 10 40 ua v resetih reset* input high voltage 2.7 vdd33 + 0.5 v v resetil reset* input low voltage gnd - 0.5 0.5 v i resetpu reset* pull up current v in = 0v 10 40 ua v testih bscan input high voltage 2.0 vdd 25 + 0.5 v v testil bscan input low voltage gnd - 0.5 0.5 v i testpd bscan pull down current v in = 2.5v 10 40 ua v xiih xi (for clock input) input high voltage 2.6 vdd33 + 0.5 v v xiil xi (for clock input) input low voltage gnd - 0.5 0.6 v v miscaoh enavd d, enabkl output high voltage i oh = - 6.5ma vdd - 0.2 v v miscaol enavdd, enabkl output low voltage i ol = 9.0ma 0.2 v notes: 1. v sdol is the spd output low voltage when transmitting from internal registers, not from ddc or eeprom. 2. v spih and v spil are the s erial port (spc and spd) input low voltage when transmitting to internal registers. separate requirements may exist for transmission to the ddc and eeprom. 3. v sd_ddcol is the output low voltage at the spd pin when the voltage at sd_ddc or sd_eprom is v inl . m aximum output voltage has been calculated with a worst case pullup of 4.0k ? to 2.5v on spd. 4. v ddcol is the output low voltage at the sc_ddc and sd_ddc pins when the voltage at spc and spd is v inl . maximum output voltage has been calculated with 5.6k pullup to 3.3v on sc_ddc and sd_ddc. 5. v epromol is the output low voltage at the sc_eprom and sd_eprom pins when the voltage at spc and spd is v inl . maximum output voltage has been calculated with 5.6k ? pullup to 5v on sc_eprom and sd_eprom.
chrontel ch7 3 0 8b 16 201 - 00 00 - 0 6 4 rev. 3. 0 , 0 5 / 1 1 /20 11 4.5 ac speci fications symbol description test condition min typ max unit ui data sdvo receiver unit interval for data channels typ. C f sdvob_clk sdvo clk input frequency 100 200 mhz f pixel sdvo receiver pixel freq uency 25 200 mhz f symbol sdvo receiver symbol frequency 1 2 ghz t rx - eye sdvo receiver minimum eye width 0.4 ui t rx - eye - jitter sdvo receiver max. time between jitter median and max. deviation from median 0.3 ui v rx - cm - acp sdvo receiver ac peak common mode input voltage 150 mv rl rx - diff differential return loss 50mhz C rl rx - cm common mode return loss 50mhz C t skew sdvo receiver total lane to lane skew of inputs across all lanes 2 ns c xi xi input capacitanc e 15 pf f tol xi xi input clock frequency tolerance (when crystal not used) - 1000 +1000 ppm dc xi xi input clock duty cycle (when crystal not used) 45 55 % t spr spc, spd rise time (20% - 80%) standard mode 100k fast mode 400k 1m running speed 100 0 300 150 ns ns ns t spf spc, spd fall time (20% - 80%) standard mode 100k fast mode 400k 1m running speed 300 300 150 ns ns ns t promr sc_prom, sd_prom rise time (20% - 80%) fast mode 400k 300 ns t promf sc_prom, sd_prom rise time (20% - 80%) fast mod e 400k 300 ns t ddcr sc_ddc, sd_ddc rise time (20% - 80%) standard mode 100k 1000 ns t ddcf sc_ddc, sd_ddc fall time (20% - 80%) standard mode 100k 300 ns
chrontel ch7 3 0 8b 201 - 0000 - 0 6 4 rev. 3. 0 , 0 5 / 1 1 /20 11 17 symbol description test condition min typ max unit t ddcr - delay 1 sc_ddc, sd_ddc rise time delay (50%) standard mode 100k 0 ns t ddcf - delay 1 sc_ ddc, sd_ddc fall time delay (50%) standard mode 100k 3 ns notes: 1. refers to the figure below, the delay refers to the time pass through the internal switches. figure 6 : ddc C spc/spd cir cuit r=5k 3.3v typ. 2.5v typ. to spc/spd pin to ddc pin
chrontel ch7 3 0 8b 18 201 - 00 00 - 0 6 4 rev. 3. 0 , 0 5 / 1 1 /20 11 4.6 lvds output specifications the lvds specifications meet the requirements of ansi/eia/tia - 644. refer to figure 7 for definitions of parameters. symbol description test condition min typ max unit |v t | st eady state differential output magnitude for logic 1 100 ? differential load 247 453 mv | v t *| steady state differential output magnitude for logic 0 100 ? differential load 247 453 mv | v t | - | v t *| steady state magnitude of differential between logi c 1 and 0 outputs 100 ? differential load 50 mv |v os | steady state magnitude of offset voltage for logic 1 measured at centertap of two 50 ? resistors connected between outputs 1.125 1.375 v |v os *| steady state magnitude of offset voltage for log ic 0 measured at centertap of two 50 ? resistors connected between outputs 1.125 1.375 v |vos| - |vos*| steady state magnitude of offset difference between logic states measured at centertap of two 50 ? resistors connected between outputs 50 mv f llc 1 lvd s output clock frequency 25 108 mhz t ui 1 lvds data unit time interval 25mhz < f llc <108mhz 1.3 5.7 ns t r lvds data rise time t ui > 5ns 1.3ns80% vswing 0.3*t ui 1.5 ns ns t f lvds data fall time t ui > 5ns 1 .3ns20% vswing 0.3*t ui 1.5 ns ns vring voltage ringing after transition 100 ? and 5pf differential load 20% vswing note 1: corresponds to maximum pixel rate f xclk for single channel operation. dual chan nel operation is required for pixel rates greater than 108mhz.
chrontel ch7 3 0 8b 201 - 0000 - 0 6 4 rev. 3. 0 , 0 5 / 1 1 /20 11 19 4.7 lvds output timing figure 7 : ac timing for lvds outputs table 8 : ac timing for lvds outputs symbol parameter min typ max | v t | steady sta te differential output magnitude see section 4.6 v swing voltage difference between the two steady state values of output | v t | + | v t *| t ui unit time interval see section 4.6 t r rise time see section 4.6 t f fall time see section 4.6 t ui t r t f v swing v ring +/-20% v swing 0v differential 0.8 v swing 0.2 v swing -v t +v t
chrontel ch7 3 0 8b 20 201 - 00 00 - 0 6 4 rev. 3. 0 , 0 5 / 1 1 /20 11 5.0 package dimensions tab le of dimensions no. of leads symbol 64 (10 x 10 mm) a b c d e f g h i j milli - meters min 12 10 0.50 0.17 1.35 0.05 1.00 0.45 0.09 0 max 0.27 1.45 0.15 0.75 0.20 7 figure 8 : 64 pin lqfp package
chrontel ch7 3 0 8b 201 - 0000 - 0 6 4 rev. 3. 0 , 0 5 / 1 1 /20 11 21 6.0 revision history tab le 9 : revisions rev. # date section description 1.0 11/23/04 all version 1.0 1.1 12/20/04 2.2 updated panel - fitting scaler information. 4.1 updated t vps C vapor phase soldering information. 1.2 1/05/05 ordering information le ad free tape and reel part number added. 4.1 note 1 updated. 1.3 1/27/05 4.4 added v miscaoh and v miscaol dc specification data. 1.4 2/2/05 1.1, 1.2 added test pin (pin50) and description. 2.5 updated figure 4 and added reference to tb49. table 8 corrected note to which section to refer to 2.2 added wide sxga+, 1680 x 1050, to table 5 1.5 2/7/05 1.2 change descriptions for pin 11, 12, 14, 15, 60, 61 2.6 replace panen set to 1 with setactiveoutput is called. 4.4, 4.5, 4.6, 4.7 change spec. values. 4.4 changed conditions and value for v ddcol 4.5 changed definition of f pixel and value for rl rx - diff 4.6 changed parameters f llc , t ui , t r , t f . 1.61 8/8/05 all changed the maximum pixel rate to 140mp/s features, 2.2 changed the maximum upscale resolution to 1600x900 table 2 updated the table to reflect the new maximum pixel rate of 140mp/s 2.2 removed panel sizes no longer supported. ordering information added a footnote stating the current revision of the ch7308a is rev ision d and marked as xud general description the last sentence of the 2 nd paragraph was edited to avoid confusion in what is the maximum pixel rate per channel. 1.7 10/12/05 ordering information added green parts into the ordering information. 4.4 , 4.5 added serial interface ac and dc electrical specification information. 1.8 12/20/05 general description sentence mentioning supported pixel rates for dual panel lvds panels (100mp/s to 140mp/s). 3.0 register control changed the first sentence to clarify that the ch7308a is controlled by use of intel opcodes instead of register reads/writes. 2.0 1/11/2006 all text and figures modified the datasheet to include the ch7308b. features and general description added ch7308b related information in th e features section and the second paragraph of the general description section. ordering information added ch7308b ordering information. 2.1 3 /13/200 8 features add ed 1600x1200 and 1920x1200 reduced blanking resolution support . pin description pin 63 and pin 64 are changed to open table 5 add ed 1920x1200 resolution reduced blanking to table 5. 2. 2 8/5 /200 8 figure 3 added lvds clock and lvds data to figure 3. 2.3 9/22/2008 4.4 updated dc specifications . 2.4 12/2/2008 4 .2 , 4. 3. updated operati ng temperature. 2.41 3/30/2008 1.2 table 1 updated description for pin 63. 3. 0 05/10/2011 4.1, 4.2 all update ambient operating temperature to - 40 ? c to +85 ? c . remove ch7308a
chrontel ch7 3 0 8b 22 201 - 00 00 - 0 6 4 rev. 3. 0 , 0 5 / 1 1 /20 11 disclaimer this document provides technical information for the user. chron tel reserves the right to make changes at any time without notice to improve and supply the best possible product and is not responsible and does not assume any liability for misapplication or use outside the limits specified in this document. we provide no warranty for the use of our products and assume no liability for errors contained in this document. the customer should make sure that they have the most recent data sheet version. customers should take appropriate action to ensure their use of the pr oducts does not infringe upon any patents. chrontel, inc. respects valid patent rights of third parties and does not infringe upon or assist others to infringe upon such rights. chrontel products are not authorized for and should not be used within life s upport systems or nuclear facility applications without the specific written consent of chrontel. life support systems are those intended to support or sustain life and whose failure to perform when used as directed can reasonably expect to result in pers onal injury or death. ordering information part number package type number of pins voltage supply ch7308b - tf lead free - lqfp 64 2.5v, 3.3v ch7308b - tf - tr lead free - tape and reel lqfp 64 2.5v, 3.3v chrontel 2210 otoole avenue, suite 100, san jose, ca 95131 - 1326 tel: (408) 383 - 9328 fax: (408) 383 - 9338 www.chrontel.com e - mail: sales@chrontel.com ? ? ? ? 200 9 chrontel, inc. all rights reserved. printed in the u.s.a.

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